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JSA
2010
102views more  JSA 2010»
13 years 7 months ago
On reducing load/store latencies of cache accesses
— Effective address calculation for load and store instructions needs to compete for ALU with other instructions and hence extra latencies might be incurred to data cache accesse...
Yuan-Shin Hwang, Jia-Jhe Li
ICPADS
2010
IEEE
13 years 7 months ago
Fault Tolerant Network Routing through Software Overlays for Intelligent Power Grids
Control decisions of intelligent devices in critical infrastructure can have a significant impact on human life and the environment. Insuring that the appropriate data is availabl...
Christopher Zimmer, Frank Mueller
RECOMB
2012
Springer
11 years 11 months ago
Estimating the Accuracy of Multiple Alignments and its Use in Parameter Advising
We develop a novel and general approach to estimating the accuracy of protein multiple sequence alignments without knowledge of a reference alignment, and use our approach to addre...
Dan F. DeBlasio, Travis J. Wheeler, John D. Kececi...
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
14 years 9 months ago
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization
Compare CMOS Logic with Pass-Transistor Logic, a question was raised in our mind: "Does any rule exist that contains all good?" This paper reveals novel logic synthesis ...
Kuo-Hsing Cheng, Shun-Wen Cheng
FUZZIEEE
2007
IEEE
14 years 3 months ago
Toward Multiple-agent Extensions of Possibilistic Logic
— Possibilistic logic is essentially a formalism for handling qualitative uncertainty with an inference machinery that remains close to the one of classical logic. It is capable ...
Didier Dubois, Henri Prade