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13 years 7 months ago
Equalizer: A Scalable Parallel Rendering Framework
Continuing improvements in CPU and GPU performances as well as increasing multi-core processor and cluster-based parallelism demand for flexible and scalable parallel rendering sol...
Stefan Eilemann, Maxim Makhinya, Renato Pajarola
PPOPP
2009
ACM
14 years 10 months ago
Safe open-nested transactions through ownership
Researchers in transactional memory (TM) have proposed open nesting as a methodology for increasing the concurrency of transactional programs. The idea is to ignore "low-leve...
Kunal Agrawal, I.-Ting Angelina Lee, Jim Sukha
CADE
2004
Springer
14 years 10 months ago
Rewriting Logic Semantics: From Language Specifications to Formal Analysis Tools
Formal semantic definitions of concurrent languages, when specified in a well-suited semantic framework and supported by generic and efficient formal tools, can be the basis of pow...
José Meseguer, Grigore Rosu
DFT
2006
IEEE
130views VLSI» more  DFT 2006»
14 years 4 months ago
Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream
Control flow checking (CFC) is a well known concurrent checking technique for ensuring that a program’s instruction execution sequence follows permissible paths. Almost all CFC...
Federico Rota, Shantanu Dutt, Sahithi Krishna
ISPASS
2006
IEEE
14 years 4 months ago
Critical path analysis of the TRIPS architecture
Fast, accurate, and effective performance analysis is essential for the design of modern processor architectures and improving application performance. Recent trends toward highly...
Ramadass Nagarajan, Xia Chen, Robert G. McDonald, ...