d Abstract) Hagit Attiya and Eshcar Hillel Department of Computer Science, Technion The design of concurrent data structures is greatly facilitated by the availability of synchroni...
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
am analysis and has been widely studied. In this paper we consider this problem at the abstraction level of program schemas in which computations occur in the Herbrand domain of te...
Sebastian Danicic, Robert M. Hierons, Michael R. L...