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KBSE
2002
IEEE
14 years 2 months ago
What Makes Finite-State Models More (or Less) Testable?
Finite-state machine (FSM) models are commonly used to represent software with concurrent processes. Established model checking tools can be used to automatically test FSM models,...
David Owen, Tim Menzies, Bojan Cukic
EUROMICRO
2000
IEEE
14 years 1 months ago
Behavioral Specification of a Circuit Using SyncCharts: A Case Study
In this paper we propose a high-level description of the behavior of digital systems. Behaviors are specified with a graphical synchronous model: “SyncCharts”. SyncCharts supp...
Charles André, Marie-Agnès Peraldi-F...
CODES
1998
IEEE
14 years 1 months ago
A hardware/software prototyping environment for dynamically reconfigurable embedded systems
Next generation embedded systems place new demands on an efficient methodology for their design and verification. These systems have to support interaction over a network, multipl...
Josef Fleischmann, Klaus Buchenrieder, Rainer Kres...
EUROMICRO
1998
IEEE
14 years 1 months ago
Design Correctness of Digital Systems
Transformational design is aformal technique directed at design correctness. It integrates design and veriJication by the use of pre-proven behaviour preserving transformations as...
Corrie Huijs
FSTTCS
1998
Springer
14 years 1 months ago
Partial Order Reductions for Bisimulation Checking
Partial order methods have been introduced to avoid the state explosion problem in veri cation resulting from the representation of multiple interleavings of concurrent transitions...
Michaela Huhn, Peter Niebert, Heike Wehrheim