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    CODES   1998 International Workshop on Hardware/Software Co-Design
    Wall of Fame | Most Viewed CODES-1998 Paper
    CODES
    1998
    IEEE
    165views Software Engineering» more  CODES 1998»
    The construction of a retargetable simulator for an architecture template
    14 years 4 months ago
    The construction of a retargetable simulator for an architecture template
    Download  ptolemy.eecs.berkeley.edu
    Systems in the domain of high-performance video signal processing are becoming more and more programmable. We suggest an approach to design such systems that involves measuring, v...
    Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, ...
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    The construction of a retargetable simulator for an architecture template
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    Communication synthesis and HW/SW integration for embedded system design
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    3Download preprint from source128
    Schedulability analysis of heterogeneous systems for performance message sequence chart
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    Domain-specific interface generation from dataflow specifications
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    5Download preprint from source111
    A hardware/software prototyping environment for dynamically reconfigurable embedded systems
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    Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder
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    7Download preprint from source106
    Hardware/software co-design of an ATM network interface card: a case study
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    Memory size estimation for multimedia applications
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    9Download preprint from source103
    An analysis-based approach to composition of distributed embedded systems
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    Modeling reactive systems in Java
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    11Download preprint from source100
    Communication estimation for hardware/software codesign
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    12Download preprint from source97
    Combining multiple models of computation for scheduling and allocation
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    13Download preprint from source84
    Optimistic distributed timed cosimulation based on thread simulation model
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    14Download preprint from source80
    Fast dynamic analysis of complex HW/SW-systems based on abstract state machine models
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    15Download preprint from source80
    Software timing analysis using HW/SW cosimulation and instruction set simulator
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    16Download preprint from source75
    A path analysis based partitioning for time constrained embedded systems
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