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CONCUR
1999
Springer
13 years 11 months ago
Partial Order Reduction for Model Checking of Timed Automata
Abstract. The paper presents a partial order reduction method applicable to networks of timed automata. The advantage of the method is that it reduces both the number of explored c...
Marius Minea
ECBS
2009
IEEE
130views Hardware» more  ECBS 2009»
14 years 2 months ago
Validating and Dynamically Adapting and Composing Features in Concurrent Product-Lines Applications
With the pressing in-time-market towards customized services, software product lines (SPL) are increasingly characterizing most of software landscape. SPL are mainly structured th...
Nasreddine Aoumeur, Kamel Barkaoui, Gunter Saake
ISSS
2002
IEEE
103views Hardware» more  ISSS 2002»
14 years 8 days ago
A Symbolic Approach for the Combined Solution of Scheduling and Allocation
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...
Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer,...
POPL
1995
ACM
13 years 11 months ago
Default Timed Concurrent Constraint Programming
d Abstract) We extend the model of [VRV94] to express strong time-outs (and pre-emption): if an event A does not happen through time t, cause event B to happen at time t. Such con...
Vijay A. Saraswat, Radha Jagadeesan, Vineet Gupta
CONCUR
2006
Springer
13 years 9 months ago
Model Checking Quantified Computation Tree Logic
Propositional temporal logic is not suitable for expressing properties on the evolution of dynamically allocated entities over time. In particular, it is not possible to trace such...
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