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LCTRTS
2005
Springer
14 years 1 months ago
Cache aware optimization of stream programs
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...
Janis Sermulins, William Thies, Rodric M. Rabbah, ...
RTSS
2007
IEEE
14 years 1 months ago
Toward the Predictable Integration of Real-Time COTS Based Systems
The integration phase of real-time COTS-based systems is often problematic because when multiple tasks run concurrently, the interference at the bus level between cache fetching a...
Rodolfo Pellizzoni, Marco Caccamo
SIGOPS
2010
179views more  SIGOPS 2010»
13 years 2 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
ICCD
2006
IEEE
124views Hardware» more  ICCD 2006»
14 years 4 months ago
Customizable Fault Tolerant Caches for Embedded Processors
Abstract— The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embe...
Subramanian Ramaswamy, Sudhakar Yalamanchili
KBSE
2009
IEEE
14 years 2 months ago
Cache-Based Model Checking of Networked Applications: From Linear to Branching Time
Abstract—Many applications are concurrent and communicate over a network. The non-determinism in the thread and communication schedules makes it desirable to model check such sys...
Cyrille Artho, Watcharin Leungwattanakit, Masami H...