1492 search results - page 283 / 299 » Concurrent programming in VISO |
CAV
2003
Springer
13 years 11 months ago
2003
Springer
odular Abstraction Refinement Thomas A. Henzinger1 , Ranjit Jhala1 , Rupak Majumdar1 , and Shaz Qadeer2 1 University of California, Berkeley 2 Microsoft Research, Redmond Abstract....
HPCN
2000
Springer
13 years 11 months ago
2000
Springer
We build an analytical model for an application utilizing master-slave paradigm. In the model, only three architecture parameters are used: latency, bandwidth and flop rate. Instea...
ASPLOS
2009
ACM
14 years 8 months ago
2009
ACM
Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly ...
ASPLOS
2009
ACM
14 years 8 months ago
2009
ACM
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...
PPOPP
2009
ACM
14 years 8 months ago
2009
ACM
Because data races represent a hard-to-manage class of errors in concurrent programs, numerous approaches to detect them have been proposed and evaluated. We specifically consider...