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ISVLSI
2005
IEEE
157views VLSI» more  ISVLSI 2005»
14 years 17 days ago
Configurable Multiprocessors for High-Performance MPEG-4 Video Coding
We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate...
Vassilios A. Chouliaras, Tom R. Jacobs, Ashwin K. ...
IPPS
2002
IEEE
13 years 12 months ago
System-Level Analysis for MPEG-4 Decoding on a Multi-Processor Architecture
The convergence of TV and new features such as Internet and games, requires a generic media-processing platform, that enables simultaneous execution of very diverse tasks, ranging...
Egbert G. T. Jaspers, Erik B. van der Tol, Peter H...
FPL
2005
Springer
226views Hardware» more  FPL 2005»
14 years 15 days ago
A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC
A parallel MPEG-4 Simple Profile encoder for FPGA based multiprocessor System-on-Chip (SOC) is presented. The goal is a computationally scalable framework independent of platform....
Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko...
ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
14 years 29 days ago
High-level architecture exploration for MPEG4 encoder with custom parameters
Abstract - this paper proposes the use of a high-level architecture exploration method for different MPEG4 video encoders using different customization parameters. The targeted arc...
Marius Bonaciu, Aimen Bouchhima, Mohamed-Wassim Yo...
TCSV
2002
119views more  TCSV 2002»
13 years 6 months ago
VLSI architecture design of MPEG-4 shape coding
This paper presents an efficient VLSI architecture design of MPEG-4 shape coding, which is the key technology for supporting the content-based functionality of the MPEG-4 Video sta...
Hao-Chieh Chang, Yung-Chi Chang, Yi-Chu Wang, Wei-...