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DAC
2007
ACM
14 years 9 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid
ASAP
2008
IEEE
161views Hardware» more  ASAP 2008»
13 years 10 months ago
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posterio...
Yang Sun, Yuming Zhu, Manish Goel, Joseph R. Caval...
ICWS
2004
IEEE
13 years 10 months ago
Best-Practice Patterns and Tool Support for Configuring Secure Web Services Messaging
This paper presents an emerging tool for security configuration of service-oriented architectures with Web Services. Security is a major concern when implementing mission-critical...
Michiaki Tatsubori, Takeshi Imamura, Yuhichi Nakam...
PODC
1999
ACM
14 years 1 months ago
LOTEC: A Simple DSM Consistency Protocol for Nested Object Transactions
In this paper, we describe an e cient software-only Distributed Shared Memory (DSM) consistency protocol for an unconventional but important application domain - object transactio...
Peter C. J. Graham, Yahong Sui
IEEEPACT
2009
IEEE
13 years 6 months ago
Adaptive Locks: Combining Transactions and Locks for Efficient Concurrency
Transactional memory is being advanced as an alternative to traditional lock-based synchronization for concurrent programming. Transactional memory simplifies the programming mode...
Takayuki Usui, Reimer Behrends, Jacob Evans, Yanni...