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HPCA
1998
IEEE
14 years 1 months ago
PRISM: An Integrated Architecture for Scalable Shared Memory
This paper describes PRISM, a distributed sharedmemory architecture that relies on a tightly integrated hardware and operating system design for scalable and reliable performance....
Kattamuri Ekanadham, Beng-Hong Lim, Pratap Pattnai...
DCC
2000
IEEE
14 years 1 months ago
Summary Structures for Frequency Queries on Large Transaction Sets
As large-scale databases become commonplace, there has been signi cant interest in mining them for commercial purposes. One of the basic tasks that underlies many of these mining ...
Dow-Yung Yang, Akshay Johar, Ananth Grama, Wojciec...
ICFP
2008
ACM
14 years 8 months ago
Transactional events for ML
Transactional events (TE) are an approach to concurrent programming that enriches the first-class synchronous message-passing of Concurrent ML (CML) with a combinator that allows ...
Laura Effinger-Dean, Matthew Kehrt, Dan Grossman
IPPS
2007
IEEE
14 years 3 months ago
A Configuration Control Mechanism Based on Concurrency Level for a Reconfigurable Consistency Algorithm
A Reconfigurable Consistency Algorithm (RCA) is an algorithm that guarantees the consistency in Distributed Shared Memory (DSM) Systems. In a RCA, there is a Configuration Control...
Christiane V. Pousa, Luís Fabrício W...
RSP
2003
IEEE
147views Control Systems» more  RSP 2003»
14 years 2 months ago
Cache Configuration Exploration on Prototyping Platforms
We describe cache architecture, intended for prototype-oriented IC platforms, that automatically finds the best cache configuration for a particular application. The cache itself ...
Chuanjun Zhang, Frank Vahid