Cache Configuration Exploration on Prototyping Platforms

We describe cache architecture, intended for prototype-oriented IC platforms, that automatically finds the best cache configuration for a particular application. The cache itself can be configured with respect to the total size, associativity, line size, and way prediction. The cache architecture includes an explorer component that efficiently searches the large space of possible configurations for the set of points representing meaningful tradeoffs between performance and energy – the Pareto-optimal set. We provide results of experiments showing that the architecture effectively finds a good set of Pareto points for numerous Powerstone and MediaBench embedded system benchmarks. Our architecture eliminates the need for time-consuming simulations to determine the best cache configuration, and imposes little power overhead and reasonable size overhead. Keywords Configurable cache, architecture tuning, low power, low energy, embedded systems, memory hierarchy, system-level exploration....

• Type: Conference
• Year: 2003
• Where: RSP
• Authors: Chuanjun Zhang, Frank Vahid
• Keywords: Cache, Cache Architecture, Keywords Configurable Cache, Rapid System Prototyping, RSP 2003