734 search results - page 81 / 147 » Configurable Transactional Memory |
EUROSYS
2007
ACM
14 years 5 months ago
2007
ACM
We present a memory-aware load balancing (MALB) technique to dispatch transactions to replicas in a replicated database. Our MALB algorithm exploits knowledge of the working sets ...
ICCAD
2010
IEEE
13 years 6 months ago
2010
IEEE
Defect repair has become a necessary process to enhance the overall yield for memories since manufacturing a natural good memory is difficult in current memory technologies. This ...
HPCA
1999
IEEE
14 years 1 months ago
1999
IEEE
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
ISCA
1999
IEEE
14 years 1 months ago
1999
IEEE
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
ISCA
1994
IEEE
14 years 28 days ago
1994
IEEE
This paper evaluates the tradeoffs involved in the design of the software-extended memory system of Alewife, a multiprocessor architecturethat implements coherentsharedmemorythrou...