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AINA
2007
IEEE
14 years 3 months ago
Synthetic Trace-Driven Simulation of Cache Memory
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
Rahman Hassan, Antony Harris, Nigel P. Topham, Ari...
ECRTS
2004
IEEE
14 years 16 days ago
TLSF: A New Dynamic Memory Allocator for Real-Time Systems
Dynamic storage allocation (DSA) algorithms play an important role in the modern software engineering paradigms and techniques (such as object oriented programming). Using DSA inc...
Miguel Masmano, Ismael Ripoll, Alfons Crespo, Jorg...
JCP
2008
141views more  JCP 2008»
13 years 8 months ago
Leakage Controlled Read Stable Static Random Access Memories
Semiconductor manufacturing process scaling increases leakage and transistor variations, both of which are problematic for static random access memory (SRAM). Since SRAM is a criti...
Sayeed A. Badrudduza, Ziyan Wang, Giby Samson, Law...
TC
2008
13 years 8 months ago
Secure Memory Accesses on Networks-on-Chip
Security is gaining relevance in the development of embedded devices. Toward a secure system at each level of design, this paper addresses security aspects related to Network-on-Ch...
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic...
DAC
2009
ACM
14 years 9 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong