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» Considering an Organization's Memory
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DATE
2010
IEEE
110views Hardware» more  DATE 2010»
14 years 24 days ago
An RDL-configurable 3D memory tier to replace on-chip SRAM
—In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked ...
Marco Facchini, Paul Marchal, Francky Catthoor, Wi...
EUROPAR
2004
Springer
14 years 1 months ago
Visual Data Rectangular Memory
We focus on the parallel access of randomly aligned rectangular blocks of visual data. As an alternative of traditional linearly addressable memories, we suggest a memory organizat...
Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassi...
SBACPAD
2003
IEEE
137views Hardware» more  SBACPAD 2003»
14 years 1 months ago
Exploring Memory Hierarchy with ArchC
This paper presents the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, prog...
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Aze...
NN
2011
Springer
348views Neural Networks» more  NN 2011»
13 years 2 months ago
Tree-like hierarchical associative memory structures
In this letter we explore an alternative structural representation for Steinbuch-type binary associative memories. These networks offer very generous storage capacities (both asy...
João Sacramento, Andreas Wichert
IJHPCA
2010
88views more  IJHPCA 2010»
13 years 6 months ago
Madre: the Memory-Aware Data Redistribution Engine
We report on the development of a new computational framework for efficiently carrying out parallel data redistribution in a limited memory environment. This new library, MADRE (T...
Stephen F. Siegel, Andrew R. Siegel