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» Constrained physical design tuning
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OWLED
2008
13 years 11 months ago
Representing Product Designs Using a Description Graph Extension to OWL 2
Product development requires the ability to check design consistency, to verify design properties, and to answer questions about a design's possible implementations. These tas...
Henson Graves
ICCAD
2000
IEEE
109views Hardware» more  ICCAD 2000»
14 years 2 months ago
Latency-Guided On-Chip Bus Network Design
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
Milenko Drinic, Darko Kirovski, Seapahn Meguerdich...
SAC
2010
ACM
13 years 10 months ago
Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...
Pavel Ghosh, Arunabha Sen
ISVLSI
2007
IEEE
107views VLSI» more  ISVLSI 2007»
14 years 4 months ago
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis
Performance, power, and functionality, yield and manufacturability are rapidly becoming additional critical factors that must be considered at higher levels of ion. A possible sol...
Angelo P. E. Rosiello, Fabrizio Ferrandi, Davide P...
FASE
2003
Springer
14 years 3 months ago
Spatial Security Policies for Mobile Agents in a Sentient Computing Environment
Abstract. A Sentient Computing environment is one in which the system is able to perceive the state of the physical world and use this information to customise its behaviour. Mobil...
David Scott, Alastair R. Beresford, Alan Mycroft