2 search results - page 1 / 1 » Constrained planar remeshing for architecture |
GRAPHICSINTERFACE
2007
14 years 18 days ago
2007
Material limitations and fabrication costs generally run at odds with the creativity of architectural design, producing a wealth of challenging computational geometry problems. We...
DATE
2008
IEEE
14 years 5 months ago
2008
IEEE
Extending 2-D planar topologies in integrated circuits (ICs) to a 3-D implementation has the obvious benefits of reducing the overall footprint and average interconnection length,...