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CP
2004
Springer
14 years 22 days ago
Generating Robust Partial Order Schedules
This paper considers the problem of transforming a resource feasible, fixed-times schedule into a partial order schedule (POS) to enhance its robustness and stability properties. ...
Nicola Policella, Angelo Oddi, Stephen F. Smith, A...
CDC
2009
IEEE
129views Control Systems» more  CDC 2009»
14 years 2 days ago
Resource allocation for signal detection with active sensors
— We consider the problem of determining the existence of known constant signals over a set of sites, given noisy measurements obtained by a team of active sensors that can switc...
Jerome Le Ny, Michael M. Zavlanos, George J. Pappa...
JMLR
2008
150views more  JMLR 2008»
13 years 7 months ago
Discriminative Learning of Max-Sum Classifiers
The max-sum classifier predicts n-tuple of labels from n-tuple of observable variables by maximizing a sum of quality functions defined over neighbouring pairs of labels and obser...
Vojtech Franc, Bogdan Savchynskyy
TCAD
2010
88views more  TCAD 2010»
13 years 2 months ago
Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...
Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
ISPD
2012
ACM
288views Hardware» more  ISPD 2012»
12 years 2 months ago
Construction of realistic gate sizing benchmarks with known optimal solutions
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Andrew B. Kahng, Seokhyeong Kang