This paper considers the problem of transforming a resource feasible, fixed-times schedule into a partial order schedule (POS) to enhance its robustness and stability properties. ...
Nicola Policella, Angelo Oddi, Stephen F. Smith, A...
— We consider the problem of determining the existence of known constant signals over a set of sites, given noisy measurements obtained by a team of active sensors that can switc...
Jerome Le Ny, Michael M. Zavlanos, George J. Pappa...
The max-sum classifier predicts n-tuple of labels from n-tuple of observable variables by maximizing a sum of quality functions defined over neighbouring pairs of labels and obser...
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...