Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement

Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D SiGe) technique as the most important stressing mechanism for PMOS devices has opened up various optimization possibilities at circuit design stage. In this work, we exploit the active area dependence of the performance improvement achievable using S/D SiGe technology for late stage ECO timing optimization. An active area sizing aware cell-level delay model is derived which forms the basis of linear program (LP) based optimization of a design for achieving maximum performance or target performance under a timing budget. To control the magnitude of layout perturbation and ensure predictable timing improvement, a set of physical constraints for active area sizing is proposed. Further, an efficient minimum movement legalization algorithm is proposed to remove the overlaps caused by active area sizing of timing c...

• Type: Journal
• Year: 2010
• Where: TCAD
• Authors: Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
• Keywords: Active Area, Late Stage Eco, Performance Improvement, Software Engineering, TCAD 2010