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» Constraint Validation in Model Compilers
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ISPASS
2006
IEEE
14 years 1 months ago
Automatic testcase synthesis and performance model validation for high performance PowerPC processors
The latest high-performance IBM PowerPC microprocessor, the POWER5 chip, poses challenges for performance model validation. The current stateof-the-art is to use simple hand-coded...
Robert H. Bell Jr., Rajiv R. Bhatia, Lizy K. John,...
ICS
2005
Tsinghua U.
14 years 15 days ago
Improved automatic testcase synthesis for performance model validation
Performance simulation tools must be validated during the design process as functional models and early hardware are developed, so that designers can be sure of the performance of...
Robert H. Bell Jr., Lizy Kurian John
ICLP
1994
Springer
13 years 11 months ago
Compiling Intensional Sets in CLP
Constructive negation has been proved to be a valid alternative to negation as failure, especially when negation is required to have, in a sense, an `active' role. In this pa...
Paola Bruscoli, Agostino Dovier, Enrico Pontelli, ...
ISSS
1998
IEEE
117views Hardware» more  ISSS 1998»
13 years 11 months ago
HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation
The concept of retargetability enables compiler technology to keep pace with the increasing variety of domain-speci c embedded processors. In order to achieve user retargetability,...
Rainer Leupers
ISSTA
2004
ACM
14 years 13 days ago
An optimizing compiler for batches of temporal logic formulas
Model checking based on validating temporal logic formulas has proven practical and effective for numerous software engineering applications. As systems based on this approach ha...
James Ezick