Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
Malay Haldar, Anshuman Nayak, Alok N. Choudhary, P...
Abstract—Handling mobility at the transport layer is a promising approach to achieve seamless handover in the context of heterogeneous wireless access networks. In particular, fe...
Many techniques for power management employed in advanced RTL synthesis tools rely explicitly or implicitly on observability don’t-care (ODC) conditions. In this paper we presen...
Abstract— In this paper the robust behavior in some piecewise affine systems with minimally spaced transition times is studied. Such systems are found e.g. in satellites and sat...
Alexandre R. Mesquita, Karl Heinz Kienitz, Erico L...
Performance evaluation of contemporary processors is becoming increasingly difficult due to the lack of proper frameworks. Traditionally, cycle-accurate simulators have been exte...