5339 search results - page 994 / 1068 » Controllable Delay-Insensitive Processes |
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
SOSP
2003
ACM
14 years 4 months ago
2003
ACM
We describe a new architecture for Byzantine fault tolerant state machine replication that separates agreement that orders requests from execution that processes requests. This se...
ASPLOS
2010
ACM
14 years 2 months ago
2010
ACM
Contention for shared resources on multicore processors remains an unsolved problem in existing systems despite significant research efforts dedicated to this problem in the past...
CHI
2010
ACM
14 years 2 months ago
2010
ACM
Interaction designers typically revise user interface prototypes by adding unstructured notes to storyboards and screen printouts. How might computational tools increase the effic...
EUROSEC
2010
ACM
14 years 2 months ago
2010
ACM
Under conditions of heavy traffic load or sudden traffic bursts, the peak processing throughput of network intrusion detection systems (NIDS) may not be sufficient for inspecting ...