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ISCA
1996
IEEE
130views Hardware» more  ISCA 1996»
13 years 12 months ago
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
Mark Horowitz, Margaret Martonosi, Todd C. Mowry, ...
TVLSI
2008
164views more  TVLSI 2008»
13 years 7 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
ICPP
2009
IEEE
13 years 5 months ago
Using Subfiling to Improve Programming Flexibility and Performance of Parallel Shared-file I/O
There are two popular parallel I/O programming styles used by modern scientific computational applications: unique-file and shared-file. Unique-file I/O usually gives satisfactory ...
Kui Gao, Wei-keng Liao, Arifa Nisar, Alok N. Choud...
EUROSYS
2009
ACM
14 years 4 months ago
Transparent checkpoints of closed distributed systems in Emulab
Emulab is a testbed for networked and distributed systems experimentation. Two guiding principles of its design are realism and control of experimentation. There is an inherent te...
Anton Burtsev, Prashanth Radhakrishnan, Mike Hible...
SAINT
2005
IEEE
14 years 1 months ago
Design and Analysis of an e-Transaction Protocol Tailored for OCC
In this work we present a protocol ensuring the eTransaction guarantee (i.e. a recently proposed end-to-end reliability guarantee) in a Web based, three-tier transactional system....
Paolo Romano, Francesco Quaglia, Bruno Ciciani