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EUROPAR
2008
Springer
13 years 10 months ago
Optimized Pipelined Parallel Merge Sort on the Cell BE
Chip multiprocessors designed for streaming applications such as Cell BE offer impressive peak performance but suffer from limited bandwidth to offchip main memory. As the number o...
Jörg Keller, Christoph W. Kessler
ICPP
2009
IEEE
13 years 6 months ago
Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this c...
Matteo Monchiero, Ramon Canal, Antonio Gonzá...
CF
2008
ACM
13 years 10 months ago
DMA-based prefetching for i/o-intensive workloads on the cell architecture
Recent advent of the asymmetric multi-core processors such as Cell Broadband Engine (Cell/BE) has popularized the use of heterogeneous architectures. A growing body of research is...
M. Mustafa Rafique, Ali Raza Butt, Dimitrios S. Ni...
IJPP
2010
156views more  IJPP 2010»
13 years 5 months ago
ForestGOMP: An Efficient OpenMP Environment for NUMA Architectures
Exploiting the full computational power of current hierarchical multiprocessor machines requires a very careful distribution of threads and data among the underlying non-uniform ar...
François Broquedis, Nathalie Furmento, Bric...
IISWC
2009
IEEE
14 years 3 months ago
Understanding PARSEC performance on contemporary CMPs
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
Major Bhadauria, Vincent M. Weaver, Sally A. McKee