Sciweavers

275 search results - page 49 / 55
» Core architecture optimization for heterogeneous chip multip...
Sort
View
TCAD
2008
110views more  TCAD 2008»
13 years 7 months ago
A Reactive and Cycle-True IP Emulator for MPSoC Exploration
The design of MultiProcessor Systems-on-Chip (MPSoC) emphasizes intellectual-property (IP)-based communication-centric approaches. Therefore, for the optimization of the MPSoC inte...
Shankar Mahadevan, Federico Angiolini, Jens Spars&...
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
14 years 2 months ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha
JPDC
2008
147views more  JPDC 2008»
13 years 8 months ago
A Grid-based Virtual Reactor: Parallel performance and adaptive load balancing
This paper addresses the problem of porting distributed parallel applications to the Grid. One of the challenges we address is the change from static homogeneous cluster environmen...
Vladimir Korkhov, Valeria V. Krzhizhanovskaya, Pet...
LCPC
2005
Springer
14 years 2 months ago
Compiler Supports and Optimizations for PAC VLIW DSP Processors
Abstract. Compiler is substantially regarded as the most essential component in the software toolchain to promote a successful processor design. This paper describes our preliminar...
Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Y...
HPCA
2009
IEEE
14 years 9 months ago
Design and implementation of software-managed caches for multicores with local memory
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
Sangmin Seo, Jaejin Lee, Zehra Sura