275 search results - page 8 / 55 » Core architecture optimization for heterogeneous chip multip... |
IEEEPACT
2008
IEEE
14 years 3 months ago
2008
IEEE
While technology trends have ushered in the age of chip multiprocessors (CMP) and enabled designers to place an increasing number of cores on chip, a fundamental question is what ...
SBACPAD
2007
IEEE
14 years 3 months ago
2007
IEEE
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
ISCA
2007
IEEE
14 years 3 months ago
2007
IEEE
Chip multiprocessors (CMPs) are now commonplace, and the number of cores on a CMP is likely to grow steadily. However, in order to harness the additional compute resources of a CM...
ICCD
2011
IEEE
12 years 8 months ago
2011
IEEE
—A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. ...
PDP
2011
IEEE
13 years 11 days ago
2011
IEEE
—Energy-efficiency is becoming one of the most critical issues in embedded system design. In Network-on-Chip (NoC) based heterogeneous Multiprocessor Systems, the energy consump...