Sciweavers

548 search results - page 61 / 110
» Core-Selectability in Chip Multiprocessors
Sort
View
DSD
2010
IEEE
141views Hardware» more  DSD 2010»
15 years 2 months ago
Adaptive Beamforming Using the Reconfigurable MONTIUM TP
Until a decade ago, the concept of phased array beamforming was mainly implemented with mechanical or analog solutions. Today, digital hardware has become powerful enough to perfor...
Marcel D. van de Burgwal, Kenneth C. Rovers, Koen ...
IPPS
2010
IEEE
15 years 1 months ago
A PRAM-NUMA model of computation for addressing low-TLP workloads
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
Martti Forsell
139
Voted
IPPS
2010
IEEE
15 years 1 months ago
Fine-grained QoS scheduling for PCM-based main memory systems
With wide adoption of chip multiprocessors (CMPs) in modern computers, there is an increasing demand for large capacity main memory systems. The emerging PCM (Phase Change Memory) ...
Ping Zhou, Yu Du, Youtao Zhang, Jun Yang 0002
TPDS
2010
125views more  TPDS 2010»
14 years 10 months ago
Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level
The importance of transient faults is predicted to grow due to current technology trends of increased scale of integration. One of the components that will be significantly affecte...
Ricardo Fernández Pascual, José M. G...
HPCA
2011
IEEE
14 years 7 months ago
CloudCache: Expanding and shrinking private caches
The number of cores in a single chip multiprocessor is expected to grow in coming years. Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilizatio...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers