548 search results - page 64 / 110 » Core-Selectability in Chip Multiprocessors |
161
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EUROPAR
2010
Springer
15 years 4 months ago
2010
Springer
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
132
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AHS
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
131
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IPPS
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper explores thread scheduling on an increasingly popular architecture: chip multiprocessors with simultaneous multithreading cores. Conventional multiprocessor scheduling,...
141
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CPAIOR
2006
Springer
15 years 7 months ago
2006
Springer
Abstract. In this paper we introduce a complex allocation and scheduling problem for variable voltage Multi-Processor System-on-Chip (MPSoC) platforms. We propose a methodology to ...
139
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ETS
2010
IEEE
15 years 5 months ago
2010
IEEE
Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking g...