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RR
2010
Springer
15 years 22 days ago
Processing RIF and OWL2RL within DLVHEX
We present an extension of the DLVHEX system to support RIF-Core, a dialect of W3C’s Rule Interchange Format (RIF), as well as combinations of RIF-Core and OWL2RL ontologies. DLV...
Marco Marano, Philipp Obermeier, Axel Polleres
WACV
2012
IEEE
13 years 10 months ago
Dynamic and invisible messaging for visual MIMO
The growing ubiquity of cameras in hand-held devices and the prevalence of electronic displays in signage creates a novel framework for wireless communications. Traditionally, the...
Wenjia Yuan, Kristin J. Dana, Ashwin Ashok, Marco ...
117
Voted
CODES
2005
IEEE
15 years 8 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra
107
Voted
CASES
2008
ACM
15 years 4 months ago
Optimus: efficient realization of streaming applications on FPGAs
In this paper, we introduce Optimus: an optimizing synthesis compiler for streaming applications. Optimus compiles programs written in a high level streaming language to either so...
Amir Hormati, Manjunath Kudlur, Scott A. Mahlke, D...
172
Voted
CAV
1998
Springer
175views Hardware» more  CAV 1998»
15 years 6 months ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore