92 search results - page 12 / 19 » Correct-by-construction microarchitectural pipelining |
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents a hardware-based dynamic optimizer that continuously optimizes an application’s instruction stream. In continuous optimization, dataflow optimizations are p...
ISCA
2002
IEEE
14 years 12 days ago
2002
IEEE
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
APCSAC
2000
IEEE
13 years 12 months ago
2000
IEEE
This paper briefly reviews the current research into RISC microprocessor architecture, which now seems to be so complex as to make the acronym somewhat of an oxymoron. In response...
IISWC
2006
IEEE
14 years 1 months ago
2006
IEEE
— Recent advances in molecular biology have led to a continued growth in the biological information generated by the scientific community. Additionally, this area has become a m...
CGO
2003
IEEE
14 years 23 days ago
2003
IEEE
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...