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ISCA
2000
IEEE
81views Hardware» more  ISCA 2000»
14 years 6 days ago
Clock rate versus IPC: the end of the road for conventional microarchitectures
The doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scaling of the processor clock with tech...
Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckle...
ICASSP
2010
IEEE
13 years 8 months ago
Multi-modal analysis of dance performances for music-driven choreography synthesis
We propose a framework for modeling, analysis, annotation and synthesis of multi-modal dance performances. We analyze correlations between music features and dance figure labels ...
Ferda Ofli, Engin Erzin, Yucel Yemez, A. Murat Tek...
BMVC
2002
13 years 10 months ago
Practical Generation of Video Textures using the Auto-Regressive Process
Recently, there have been several attempts at creating `video textures', that is, synthesising new (potentially infinitely long) video clips based on existing ones. One way t...
Neill W. Campbell, Colin J. Dalton, David P. Gibso...
JMLR
2010
157views more  JMLR 2010»
13 years 6 months ago
Kronecker Graphs: An Approach to Modeling Networks
How can we generate realistic networks? In addition, how can we do so with a mathematically tractable model that allows for rigorous analysis of network properties? Real networks ...
Jure Leskovec, Deepayan Chakrabarti, Jon M. Kleinb...
ISLPED
1997
ACM
114views Hardware» more  ISLPED 1997»
14 years 2 hour ago
Cycle-accurate macro-models for RT-level power analysis
 In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RTlevel power analysis. The proposed macro-model predicts not only...
Qinru Qiu, Qing Wu, Massoud Pedram, Chih-Shun Ding