237 search results - page 22 / 48 » Cost-Efficient Memory Architecture Design of NAND Flash Memo... |
DAC
2006
ACM
14 years 1 months ago
2006
ACM
Reduction of the on-chip memory size is a key issue in video codec system design. Because video codec applications involve complex algorithms that are both data-intensive and cont...
ACSAC
2008
IEEE
14 years 2 months ago
2008
IEEE
Main memory contains transient information for all resident applications. However, if memory chip contents survives power-off, e.g., via freezing DRAM chips, sensitive data such a...
OSDI
1994
ACM
13 years 9 months ago
1994
ACM
Mobile computers such as notebooks, subnotebooks, and palmtops require low weight, low power consumption, and good interactive performance. These requirements impose many challeng...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...
RTAS
2010
IEEE
13 years 6 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...