We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
We explore the average-case “Vickrey” cost of structures in a random setting: the Vickrey cost of a shortest path in a complete graph or digraph with random edge weights; the V...
We show that the perfect matching problem is in the complexity class SPL in the nonuniform setting. This provides a better upper bound on the complexity of the matching problem, a...
This paper surveys recent results in the area of virtual path layout in ATM networks. We present a model for the theoretical study of these layouts the model amounts to covering t...
This paper presents a range of quantitative extensions for the temporal logic CTL. We enhance temporal modalities with the ability to constrain the number of states satisfying cert...