46 search results - page 4 / 10 » Cox-Rower Architecture for Fast Parallel Montgomery Multipli... |
ISPAN
2005
IEEE
14 years 1 months ago
2005
IEEE
Most high-end switches use an input-queued or a combined input- and output-queued architecture. The switch fabrics of these architectures commonly use an iterative scheduling syst...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant ove...
PDPTA
2007
13 years 9 months ago
2007
- In this paper, we study the algorithm design aspects of three newly developed spin-wave architectures. The architectures are capable of simultaneously transmitting multiple signa...
PC
2002
13 years 7 months ago
2002
We present a new parallel algorithm to compute an exact triangularization of large square or rectangular and dense or sparse matrices in any field. Using fast matrix multiplicatio...
HPDC
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper describes work in progress to develop a standard for interoperability among high-performance scientific components. This research stems from growing recognition that th...