Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal

Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional multi-context (MC) switch with high scalability. The transistor count of the proposed MC-switch is reduced to 7% in comparison with that of a SRAM-based one.

• Type: Conference
• Year: 2006
• Where: IPPS
• Authors: Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama
• Keywords: Bit Forming Configuration, Context Switching Signal, Distributed And Parallel Computing, IPPS 2006, Multiple Memory Bits