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ATS
2005
IEEE
118views Hardware» more  ATS 2005»
14 years 1 months ago
Partial Gating Optimization for Power Reduction During Test Application
Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to...
Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ra...
GLVLSI
2002
IEEE
136views VLSI» more  GLVLSI 2002»
14 years 22 days ago
Test generation for resistive opens in CMOS
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...
Arun Krishnamachary, Jacob A. Abraham
ITC
1995
IEEE
122views Hardware» more  ITC 1995»
13 years 11 months ago
A Fault Model and a Test Method for Analog Fuzzy Logic Circuits
A nalog circuit implementations of fuzzy logic are characterized by performing logical connectives of analog signals. They can be considered as generalization of digital circuits ...
Stefan Weiner
TSE
2011
180views more  TSE 2011»
13 years 2 months ago
Developing a Single Model and Test Prioritization Strategies for Event-Driven Software
—Event-Driven Software (EDS) can change state based on incoming events; common examples are GUI and web applications. These EDS pose a challenge to testing because there are a la...
Renée C. Bryce, Sreedevi Sampath, Atif M. M...
NAACL
1994
13 years 9 months ago
A New Approach to Word Sense Disambiguation
This paper presents and evaluates models created according to a schema that provides a description of the joint distribution of the values of sense tags and contextual features th...
Rebecca F. Bruce, Janyce Wiebe