Sciweavers

27 search results - page 3 / 6
» CrossTalk: scalably interconnecting instant messaging networ...
Sort
View
MICRO
2006
IEEE
155views Hardware» more  MICRO 2006»
14 years 26 days ago
In-Network Cache Coherence
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
Noel Eisley, Li-Shiuan Peh, Li Shang
INFOCOM
2005
IEEE
14 years 13 days ago
FISSIONE: a scalable constant degree and low congestion DHT scheme based on Kautz graphs
Abstract— The distributed hash table (DHT) scheme has become the core component of many large-scale peer-to-peer networks. Degree, diameter, and congestion are important measures...
Dongsheng Li, Xicheng Lu, Jie Wu
OPODIS
2007
13 years 8 months ago
A Decentralized, Scalable, and Autonomous Grid Monitoring System
Abstract. Grid monitoring systems collect a substantial amount of information on the infrastructure’s status in order to perform various tasks, more commonly to provide a better ...
Laurent Baduel, Satoshi Matsuoka
CASES
2008
ACM
13 years 8 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
AINA
2007
IEEE
14 years 1 months ago
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
Antonio Flores, Juan L. Aragón, Manuel E. A...