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» Crosstalk noise in FPGAs
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ET
2002
97views more  ET 2002»
13 years 7 months ago
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results
Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This...
Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
ISQED
2003
IEEE
104views Hardware» more  ISQED 2003»
14 years 27 days ago
Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis
As the portion of coupling capacitance increases in smaller process geometries, accurate coupled noise analysis is becoming more important in current design methodologies. We prop...
Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-...
ICCAD
2007
IEEE
105views Hardware» more  ICCAD 2007»
14 years 1 months ago
Victim alignment in crosstalk aware timing analysis
Modeling the effect of coupling noise on circuit delay is a key issue in static timing analysis (STA) and involves the “victimaggressor alignment” problem. As delay-noise depe...
Ravikishore Gandikota, Kaviraj Chopra, David Blaau...
CORR
2008
Springer
79views Education» more  CORR 2008»
13 years 7 months ago
New Outer Bounds on the Capacity Region of Gaussian Interference Channels
Abstract-- An outer bound on the capacity region of the twouser Gaussian interference channel is derived. The bound shows that for low power and small crosstalk coefficients the su...
Xiaohu Shang, Gerhard Kramer, Biao Chen
ISLPED
2007
ACM
138views Hardware» more  ISLPED 2007»
13 years 9 months ago
Power optimal MTCMOS repeater insertion for global buses
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
Hanif Fatemi, Behnam Amelifard, Massoud Pedram