86 search results - page 5 / 18 » Custom Data Layout for Memory Parallelism |
PATMOS
2000
Springer
13 years 11 months ago
2000
Springer
Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, esp...
EUROPAR
2003
Springer
14 years 21 days ago
2003
Springer
We introduce a software/hardware scheme called the Field Array Compression Technique (FACT) which reduces cache misses due to recursive data structures. Using a data layout transfo...
FPL
2009
Springer
14 years 3 days ago
2009
Springer
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) ...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Due to the complexity associated with developing parallel applications, scientists and engineers rely on highlevel software libraries such as PETSc, ScaLAPACK and PESSL to ease th...