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ICDE
1999
IEEE
113views Database» more  ICDE 1999»
14 years 8 months ago
Parallel Algorithms for Computing Temporal Aggregates
The ability to model the temporal dimension is essential to many applications. Furthermore, the rate of increase in database size and response time requirements has outpaced advan...
Jose Alvin G. Gendrano, Bruce C. Huang, Jim M. Rod...
GLVLSI
2003
IEEE
310views VLSI» more  GLVLSI 2003»
14 years 22 days ago
54x54-bit radix-4 multiplier based on modified booth algorithm
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-se...
SBCCI
2005
ACM
185views VLSI» more  SBCCI 2005»
14 years 1 months ago
Automatic generation of test sets for SBST of microprocessor IP cores
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
Ernesto Sánchez, Matteo Sonza Reorda, Giova...
INFOCOM
2002
IEEE
14 years 11 days ago
ASCENT: Adaptive Self-Configuring sEnsor Networks Topologies.
—Advances in microsensor and radio technology will enable small but smart sensors to be deployed for a wide range of environmental monitoring applications. The low per-node cost ...
Alberto Cerpa, Deborah Estrin
DAC
2009
ACM
14 years 8 months ago
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
This paper presents a technique to improve the storage density of spin-torque transfer (STT) magnetoresistive random access memory (MRAM) in the presence of significant magnetic t...
Wei Xu, Yiran Chen, Xiaobin Wang, Tong Zhang