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» Customized Instruction-Sets for Embedded Processors
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DATE
2011
IEEE
223views Hardware» more  DATE 2011»
13 years 8 days ago
Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
Martin Schoeberl, Pascal Schleuniger, Wolfgang Puf...
CODES
2005
IEEE
14 years 2 months ago
Designing real-time H.264 decoders with dataflow architectures
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
Youngsoo Kim, Suleyman Sair
IPPS
2007
IEEE
14 years 2 months ago
Splice: A Standardized Peripheral Logic and Interface Creation Engine
Recent advancements in FPGA technology have allowed manufacturers to place general-purpose processors alongside user-configurable logic gates on a single chip. At first glance, ...
Justin Thiel, Ron K. Cytron
CODES
2002
IEEE
14 years 1 months ago
Codesign-extended applications
We challenge the widespread assumption that an embedded system’s functionality can be captured in a single specification and then partitioned among software and custom hardware ...
Brian Grattan, Greg Stitt, Frank Vahid
CODES
2008
IEEE
13 years 10 months ago
Software optimization for MPSoC: a mpeg-2 decoder case study
Using traditional software profiling to optimize embedded software in an MPSoC design is not reliable. With multiple processors running concurrently and programs interacting, trad...
Eric Cheung, Harry Hsieh, Felice Balarin