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» DAPR: Design Automation for Partially Reconfigurable FPGAs
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DATE
2002
IEEE
83views Hardware» more  DATE 2002»
14 years 1 months ago
Reconfigurable SoC - What Will it Look Like?
The argument against ASIC SoCs is that they have always taken too long and cost too much to design. As new process technologies come on line, the issue of inflexible, unyielding d...
J. Bryan Lewis, Ivo Bolsens, Rudy Lauwereins, Chri...
IPPS
2007
IEEE
14 years 2 months ago
Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems
When reconfigurable devices are used in modern embedded systems and their capability to adapt to changing application requirements becomes an issue, comprehensive modeling and de...
Florian Dittmann, Marcelo Götz, Achim Rettber...
FPL
2004
Springer
103views Hardware» more  FPL 2004»
14 years 1 months ago
Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs
Abstract. Function evaluation is at the core of many compute-intensive applications which perform well on reconfigurable platforms. Yet, in order to implement function evaluation ...
Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne L...
FCCM
2009
IEEE
170views VLSI» more  FCCM 2009»
13 years 6 months ago
Generic Software Framework for Adaptive Applications on FPGAs
Adaptive systems are set to become more mainstream, as numerous practical applications in the communications domain emerge. FPGAs offer an ideal implementation platform, combining...
Suhaib A. Fahmy, Jorg Lotze, Juanjo Noguera, Linda...
FPL
2005
Springer
140views Hardware» more  FPL 2005»
14 years 2 months ago
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial rec...
Usama Malik, Oliver Diessel