39 search results - page 7 / 8 » DELTEST: Deterministic Test Generation for Gate-Delay Faults |
DATE
2000
IEEE
14 years 29 days ago
2000
IEEE
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
CEC
2005
IEEE
14 years 2 months ago
2005
IEEE
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
DDECS
2006
IEEE
14 years 2 months ago
2006
IEEE
- Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words i...
ITC
1996
IEEE
14 years 21 days ago
1996
IEEE
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
VLSID
1997
IEEE
14 years 22 days ago
1997
IEEE
The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as e...