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» DNS performance and the effectiveness of caching
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MICRO
2007
IEEE
188views Hardware» more  MICRO 2007»
14 years 2 months ago
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Fal...
ISCA
2007
IEEE
149views Hardware» more  ISCA 2007»
14 years 2 months ago
An effective hybrid transactional memory system with strong isolation guarantees
We propose signature-accelerated transactional memory (SigTM), a hybrid TM system that reduces the overhead of software transactions. SigTM uses hardware signatures to track the r...
Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Au...
VEE
2006
ACM
116views Virtualization» more  VEE 2006»
14 years 1 months ago
Relative factors in performance analysis of Java virtual machines
Many new Java runtime optimizations report relatively small, single-digit performance improvements. On modern virtual and actual hardware, however, the performance impact of an op...
Dayong Gu, Clark Verbrugge, Etienne M. Gagnon
CGO
2005
IEEE
14 years 1 months ago
Performance of Runtime Optimization on BLAST
Optimization of a real world application BLAST is used to demonstrate the limitations of static and profile-guided optimizations and to highlight the potential of runtime optimiz...
Abhinav Das, Jiwei Lu, Howard Chen, Jinpyo Kim, Pe...
IPPS
2000
IEEE
14 years 3 days ago
Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...
Jim Nilsson, Fredrik Dahlgren