148 search results - page 19 / 30 » DRAMSim2: A Cycle Accurate Memory System Simulator |
JUCS
2000
13 years 7 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
WOSP
2010
ACM
14 years 2 months ago
2010
ACM
Nowadays the 2-Phase-Locking (2PL) concurrency control algorithm still plays a core rule in the construction of transactional systems (e.g. database systems and transactional memo...
ACMMSP
2004
ACM
14 years 1 months ago
2004
ACM
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
ASPLOS
2004
ACM
14 years 1 months ago
2004
ACM
This paper introduces a compiler-orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. ...
MOBIHOC
2009
ACM
14 years 8 months ago
2009
ACM
Location-free boundary recognition is crucial and critical for many fundamental network functionalities in wireless ad hoc and sensor networks. Previous designs, often coarse-grai...