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ISSS
2000
IEEE
91views Hardware» more  ISSS 2000»
14 years 2 days ago
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
Tony Givargis, Frank Vahid, Jörg Henkel
SIGMOD
2003
ACM
127views Database» more  SIGMOD 2003»
14 years 7 months ago
Cache-and-Query for Wide Area Sensor Databases
Webcams, microphones, pressure gauges and other sensors provide exciting new opportunities for querying and monitoring the physical world. In this paper we focus on querying wide ...
Amol Deshpande, Suman Kumar Nath, Phillip B. Gibbo...
CF
2008
ACM
13 years 9 months ago
A modular 3d processor for flexible product design and technology migration
The current methodology used in mass-market processor design is to create a single base microarchitecture (e.g., Intel's "Core"or AMD's"K8") that is ...
Gabriel H. Loh
PODC
1998
ACM
13 years 12 months ago
Persistent Messages in Local Transactions
: We present a new model for handling messages and state in a distributed application that we call Messages in Local Transactions (MLT). Under this model, messages and data are not...
David E. Lowell, Peter M. Chen
MICRO
1997
IEEE
82views Hardware» more  MICRO 1997»
13 years 12 months ago
Procedure Based Program Compression
Cost and power consumption are two of the most important design factors for many embedded systems, particularly consumer devices. Products such as Personal Digital Assistants, pag...
Darko Kirovski, Johnson Kin, William H. Mangione-S...