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» DYNORA: A New Caching Technique
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DATE
2003
IEEE
94views Hardware» more  DATE 2003»
14 years 29 days ago
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors
Modern embedded processors use data caches with higher and higher degrees of associativity in order to increase performance. A set–associative data cache consumes a significant...
Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru...
IEEEPACT
2005
IEEE
14 years 1 months ago
Trace Cache Sampling Filter
This paper presents a new technique for efficient usage of small trace caches. A trace cache can significantly increase the performance of wide out-oforder processors, but to be e...
Michael Behar, Avi Mendelson, Avinoam Kolodny
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
14 years 2 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
WCE
2007
13 years 8 months ago
Modified Energy Efficient Cache Invalidation Algorithm in Mobile Environment
– Maintenance of the cache consistency is a complicated issue in the wireless mobile environment. Caching of frequently accessed data items on the node can reduce the bandwidth r...
S. Sankara Gomathi, S. Krishnamurthi
ESOP
1999
Springer
13 years 12 months ago
Dynamic Programming via Static Incrementalization
Abstract. Dynamicprogramming is an importantalgorithm design technique. It is used for solving problems whose solutions involve recursively solving subproblems that share subsubpro...
Yanhong A. Liu, Scott D. Stoller