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LCTRTS
2009
Springer
14 years 2 months ago
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE)
Instruction fetch behavior has been shown to be very regular and predictable, even for diverse application areas. In this work, we propose the Lookahead Instruction Fetch Engine (...
Stephen Roderick Hines, Yuval Peress, Peter Gavin,...
TVLSI
2008
153views more  TVLSI 2008»
13 years 7 months ago
Characterization of a Novel Nine-Transistor SRAM Cell
Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors...
Zhiyu Liu, Volkan Kursun
HPCA
2009
IEEE
14 years 8 months ago
Criticality-based optimizations for efficient load processing
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Pr...
Samantika Subramaniam, Anne Bracy, Hong Wang 0003,...
ECRTS
2007
IEEE
14 years 2 months ago
WCET-Directed Dynamic Scratchpad Memory Allocation of Data
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the difference with caches, allocation of data to scratchpad memory must be handled by...
Jean-François Deverge, Isabelle Puaut
RTAS
2010
IEEE
13 years 6 months ago
DARTS: Techniques and Tools for Predictably Fast Memory Using Integrated Data Allocation and Real-Time Task Scheduling
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
Sangyeol Kang, Alexander G. Dean