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ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
14 years 22 hour ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
ANCS
2009
ACM
13 years 5 months ago
EINIC: an architecture for high bandwidth network I/O on multi-core processors
This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacit...
Guangdeng Liao, Laxmi N. Bhuyan, Danhua Guo, Steve...
HPDC
2005
IEEE
14 years 1 months ago
Collective caching: application-aware client-side file caching
Parallel file subsystems in today’s high-performance computers adopt many I/O optimization strategies that were designed for distributed systems. These strategies, for instance...
Wei-keng Liao, Kenin Coloma, Alok N. Choudhary, Le...
COMCOM
2002
124views more  COMCOM 2002»
13 years 7 months ago
Thin-client Web access patterns: Measurements from a cache-busting proxy
This paper describes a new technique for measuring Web client request patterns and analyzes a large client trace collected using the new method. In this approach a modified proxy ...
Terence Kelly
ISCAS
2007
IEEE
132views Hardware» more  ISCAS 2007»
14 years 2 months ago
High Read Stability and Low Leakage Cache Memory Cell
- Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct access to the data storage nodes through the bit lines...
Zhiyu Liu, Volkan Kursun