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» Data Criticality in Network-On-Chip Design
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HIPEAC
2009
Springer
14 years 4 months ago
Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors
Process variations, which lead to timing and power variations across identically-designed components, have been identified as one of the key future design challenges by the semico...
Yang Ding, Mahmut T. Kandemir, Mary Jane Irwin, Pa...
ICPPW
2008
IEEE
14 years 4 months ago
Non-Contiguous I/O Support for Object-Based Storage
The access patterns performed by disk-intensive applications vary widely, from simple contiguous reads or writes through an entire file to completely unpredictable random access....
Dennis Dalessandro, Ananth Devulapalli, Pete Wycko...
WCNC
2008
IEEE
14 years 4 months ago
Performance Improvement for Multichannel HARQ Protocol in Next Generation WiMAX System
Hybrid automatic repeat-request (HARQ) is critical to an IEEE 802.16e OFDMA network, as it can significantly improve the reliability of wireless link. However, as revealed by our...
Zhifeng Tao, Anfei Li, Jinyun Zhang, Toshiyuki Kuz...
GLOBECOM
2006
IEEE
14 years 3 months ago
Linear Coherent Decentralized Estimation
Abstract—We consider the distributed estimation of an unknown vector signal in a resource constrained sensor network with a fusion center. Due to power and bandwidth limitations,...
Jinjun Xiao, Shuguang Cui, Zhi-Quan Luo, Andrea J....
ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
14 years 3 months ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang